The present invention relates generally to digital phase detector circuits. More particularly, the present invention relates to a digital phase detector circuit capable of stable operation at relatively high frequencies.
The prior art is replete with digital phase detector designs and various applications for such designs. Phase detectors are commonly used in phase locked loop (PLL) circuits to synchronize a received digital data signal to a digital clock signal. PLL circuits are often used in digital data communication systems.
FIG. 1 depicts a basic PLL circuit 100. PLL circuit 100 includes a phase detector 102, which receives a digital data input signal and generates a digital data output signal. Phase detector 102 also receives a digital clock signal and generates a phase output signal and a reference output signal. The phase output signal is generated in response to the timing offset between the incoming data signal and the clock signal. PLL circuit 100 employs a filtering and integrating circuit 104 for the phase output signal and a filtering and integrating circuit 106 for the reference output signal. The processed phase and reference output signals are combined in a summer 108 and the combined signal is used as a control signal for a voltage controlled oscillator (VCO) 110. The VCO 110 produces the clock signal, and the frequency of the clock signal is varied by the VCO 110 in an attempt to optimize the alignment between the data signal and the clock signal.
One well known phase detector circuit is disclosed in U.S. Pat. No. 4,535,459, issued Aug. 13, 1985 to Hogge. FIG. 2 is a schematic representation of the fundamental Hogge detector circuit elements. The Hogge detector generally includes a first latch 202 connected in series with a second latch 204. Latch 202 receives the digital input signal and a clock signal. Latch 204 receives the output of latch 202 and an inverse clock signal. The phase output is generated by a first exclusive OR (XOR) gate 206 and the reference output signal is generated by a second XOR gate 208.
FIG. 3 illustrates various signals associated with the Hogge detector shown in FIG. 2. Several transition edges are duplicated in FIG. 3 to represent different phase possibilities associated with the incoming data and the different phase possibilities associated with data passed through a practical latch. FIG. 3 depicts a condition where the clock signal 304 is early with respect to the data signal 302. In response to this condition, the Hogge detector generates relatively narrow pulses for the phase output signal 306. Depending upon the alignment between the data signal and the clock signal, the pulses in the phase output signal 306 become wider or narrower.
The relatively narrow pulses generated by the Hogge detector can be problematic in high speed applications (e.g., 10 Gbps data rate). As mentioned above, the reference output pulses may approach a zero width as the transition edges of the data signal approach the transition edges of the clock signal. Practical devices become nonlinear and may fail under such conditions. Consequently, the phase output signal may be erroneously generated or the PLL may become unstable.
In addition, the Hogge detector requires a digital clock having a frequency equal to the bit rate of the incoming digital data stream. For example, if the incoming digital data is transmitted at 10 kbps, then the Hogge detector must use a digital clock having a nominal frequency of 10 kHz. This constraint requires higher frequency oscillators and clock drivers, which in turn requires more operating power.
Another prior art phase detector, which leverages the fundamental Hogge design, employs a digital clock having a nominal frequency that is one-half the bit rate of the digital input signal. Thus, a 20 Gbps digital input signal can be processed using a 10 GHz digital clock. Although this type of phase detector relaxes the clock frequency requirement, it generates relatively narrow pulses for the phase output signal (in the same manner as the Hogge detector). Accordingly, this type of phase detector suffers from the same practical shortcomings as the conventional Hogge detector.
The present invention provides a digital phase detector circuit that is suitable for use in high speed applications. The present invention also provides a synchronization method associated with a received digital data signal. The phase detector utilizes a digital clock having a frequency that is one-half the data rate of the input signal. Furthermore, the phase detector is capable of stable operation under a variety of clock-to-data alignment conditions. Thus, the phase detector can be realized with practical digital devices having reduced timing requirements and lower speed ratings relative to the digital devices used in prior art detectors.
The above and other aspects of the present invention may be carried out in one form by a digital synchronization method. The method involves receiving a digital input signal comprising an input data pulse with a low-to-high transition edge and a high-to-low transition edge, receiving a digital clock signal comprising a clock pulse having a low-to-high transition edge and a high-to-low transition edge, and generating a phase reference component signal comprising a phase reference pulse having a low-to-high transition edge substantially aligned with the low-to-high transition edge of the input data pulse, and having a high-to-low transition edge substantially aligned with the high-to-low transition edge of the clock pulse.